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| 1/30 st7538 february 2003 n half duplex frequency shift keying (fsk) transceiver n integrated power line driver with programmable voltage and current control n programmable interface: C synchronous C asynchronous n single supply voltage (from 7.5 up to 12.5v) n very low power consumption (iq=5 ma) n integrated 5v voltage regulator (up to 100ma) with short circuit protection n 8 programmable transmission frequencies n programmable baud rate up to 4800bps n receiving sensitivity 1 mvrms n suitable to application in accordance with en 50065 cenelec specifications n carrier or preamble detection n band in use detection n programmable register with security checksum n mains zero crossing detection and synchronization n watchdog timer description the st7538 is a half duplex synchronous/asyn- chronous fsk modem designed for power line communication network applications. it operates from a single supply voltage and integrates a line driver and a 5v linear regulator. the device oper- ation is controlled by means of an internal register, programmable through the synchronous serial in- terface. additional functions as watchdog, clock output, output voltage and current control, pream- ble detection, time-out, band in use are included. realized in multipower bcdv technology that al- lows to integrate dmos, bipolar and cmos struc- tures in the same chip. tqfp44 slug down ordering number: ST7538P power line fsk transceiver block diagram serial interface carrier detection pll cd/pd rxd clr/t reg/data rxtx txd regok pg vdc pavcc atop2 atop1 ato vsense cl rai rxfo test2 test3 test1 avdd dvdd avss dvss bu xout wd tout rsto mclk zcin zcout c_out cminus cplus xin digital filter fsk demod if filter tx filter filter + - filter bu dac zc osc agc ampl test alc op-amp pli vreg current control voltage control fsk modulator time base control register d03in1407
st7538 2/30 pin connection (top view) pin description n name type description 1 cd_pd digital/output carrier or preamble detect output. "1" no carrier or preamble detected "0" carrier or preamble detected 2 dvss supply digital ground 3 rxd digital/output rx data output. 4 rxtx digital/input with internal pull-up rx or tx mode selection input. "1" - rx session "0" - tx session 5 txd digital/input with internal pull-down tx data input. 6 gnd supply substrate ground (same function as pin 41) 7 tout digital/output tx time out event detection "1" - time out event occurred "0" - no time-out event occurred 8 clr/t digital/output synchronous mains access clock or control register access clock 9 bu digital/output band in use output. "1" signal within the programmed band "0" no signal within the programmed band 10 dvdd supply digital supply voltage 11 mclk digital/output master clock output 12 rsto digital/output power on or watchdog reset output 13 test 3 digital/input with internal pull-down test input. must be connected to dvss during normal operation 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 cd_pd dvss rxd rxtx txd gnd tout clr/t bu dvdd mclk rsto test3 wd zcout zcin n.c. dvss atop1 pavss atop2 pavcc n.c. test1 reg_ok c_minus c_plus n.c. c_out gnd pg reg_data n.c. cl ato sgnd xout xin avdd vsense test2 rxfo rai vdc d01in1312 12 13 14 15 16 3/30 st7538 14 wd digital/input with internal pull-up watchdog input. the internal watchdog counter is cleared on the falling edges. 15 zcout digital/output zero crossing detection output 16 zcin 1 analog/input zero crossing ac input. 17 nc floating must be connected to dvss. 18 dvss supply digital ground 19 atop1 power/output power line driver output 20 pavss supply power analog ground 21 atop2 power/output power line driver output 22 pav cc supply power supply voltage 23 cl 2 analog/input current limiting feedback. a resistor between cl and avss sets the pli current limiting value 24 ato analog/output small signal analog transmit output 25 sgnd supply analog signal ground 26 xout analog i/o crystal output- external clock input 27 xin analog input crystal oscillator input 28 avdd supply analog power supply. 29 vsense 3 analog/input output voltage sensing input for the voltage control loop 30 test2 analog/input test input must be connected sgnd 31 rxfo analog/output receiving filter output 32 rai analog/input receiving analog input 33 vdc power 5v voltage regulator output 34 nc floating must be connected to dvss. 35 test1 digital/input with internal pull-down test input. must be connected to dvss. 36 regok digital/output security checksum logic output "1" - stored data corrupted "0" - stored data ok 37 c_minus 4 analog/input op-amp inverting input. 38 c_plus 5 analog/input op-amp not inverting input. 39 nc floating must be connected to dvss 40 c_out analog/output op-amp output 41 gnd supply substrate ground (same function as pin 6) 42 pg digital/output power good logic output "1" - vdc is above 4.5v "0" - vdc is below 4.25v 43 reg_data digital/input with internal pull-down mains or control register access selector "1" - control register access "0" - mains access 44 nc floating must be connected to dvss. <1> if not used this pin must be connected to vdc <2> cannot be left floating <3> cannot be left floating <4> if not used this pin must be connected to vdc <5> if not used this pin must be tied low (sgnd or pavss or dvss) pin description (continued) n name type description st7538 4/30 absolute maximum ratings thermal data (*) mounted on multilayer pcb with a dissipating surface on the bottom side of the pcb (**) it's the same condition of the point above, without any heatsinking surface on the board. symbol parameter value unit pav cc power supply voltage -0.3 to +14 v av dd analog supply voltage -0.3 to +5.5 v dv dd digital supply voltage -0.3 to +5.5 v av ss /dv ss voltage between av ss and dv ss -0.3 to +0.3 v v i digital input voltage dv ss - 0.3 to dv dd +0.3 v v o digital output voltage dv ss - 0.3 to dv dd +0.3 v i o digital output current -2 to +2 ma v sense voltage range at vsense input av ss - 0.3 to av dd +0.3 v rai voltage range at rai input -av dd - 0.3 to av dd +0.3 v ato output current at ato output -2 to +2 ma ato voltage range at ato output av ss - 0.3 to av dd +0.3 v atop1,2 voltage range at powered ato output av ss - 0.3 to +pav cc +0.3 v atop powered ato output current 400 marms t amb operating ambient temperature -40 to +85 c t stg storage temperature -50 to 150 c atop1 pin maximum withstanding voltage range test condition: cdf-aec-q100-002- human body model acceptance criteria: normal performance 1500 v atop2 pin 1000 v other pins 2000 v symbol parameter tqfp44 with slug unit r th-j-amb1 maximum thermal resistance junction-ambient steady state(*) 35 c/w r th-j-amb2 maximum thermal resistance junction-ambient steady state(**) 50 c/w 5/30 st7538 electrical characteristcs (avcc = dvcc = +5v, pavcc =+9 v, pavss, sgnd = dvss = 0v,-40c tamb 85c, unless otherwise specified) symbol parameter test condition min. typ. max. unit av cc , dv cc supply voltages 4.75 5 5.25 v pav cc - dv cc pav cc and dv cc relation during power-up sequence dv cc < 4.75v 0.1 1.2 v pav cc - av cc pav cc and dv cc relation during power-up sequence av cc < 4.75v 0.1 1.2 v pav cc power supply voltage 7.5 12.5 v max allowed slope during power-up 10 v/ms ai cc + di cc input supply current transmission & receiving mode 5 7 ma i pav cc powered analog supply current tx mode (no load) 30 50 marms rx mode 500 1000 m a maximum total current 370 marms digital i/o v ih high logic level input voltage 2 v v il low logic level input voltage 0.8 v v oh high logic level output voltage i oh = -2ma 3.5 v v ol low logic level output voltage i ol = 2ma 0.4 v oscillator v ihx xin high level input voltage external clock 3 v v ilx xin low level input voltage external clock 2 v dc xtal clock duty cycle external clock 40 60 % xtal crystal oscillator frequency 16 mhz tclock oscillator period (1/xtal) 62.5 ns xtal esr external oscillator esr resistance 40 ohm xtal cl external oscillator stabilization capacitance 16 pf transmitter iatop output transmitting current in programmable current limiting vsense connected though a 100pf cap to gnd; rcl=1.85k w ; r load =1 w (as in fig. 13) 250 310 370 marms v ato max carrier output ac voltage r cl = 1.85k w vsense=0v 1.75 2.3 3.5 v pp v atod c output dc voltage on ato 1.7 2.1 2.5 v hd2 ato second harmonic distortion on ato v ato = 2v pp ; fc=86khz -55 -42 db hd3 ato third harmonic distortion on ato v ato = 2v pp ; fc=86khz -52 -49 db v atop (a c ) max carrier output ac voltage for each atop1 and atop2 pins r cl = 1.85k w vsense=0v 3.5 4.6 6 v pp v atop(dc) output dc voltage on atop1 and atop2 pins 3.5 4.2 5 v pavcc vatop ac () 2 ----------------------------------- - 7.5v + 3 st7538 6/30 hd2 ato p second harmonic distortion on each atop1 and atop2 pins v atop = 4v pp no load -55 -42 db v atop = 4v pp r load =50 w (differential) carrier frequency: 132.05khz -65 -53 db hd3 ato p third harmonic distortion on each atop1 and atop2 pins v atop = 4v pp no load. -56 -49 db v atop = 4v pp r load =50 w (differential) carrier frequency: 132.05khz -65 -52 db vatop accuracy with voltage control loop active r cl = 0 w -1 +1 gst gst alc gain step control loop gain step 0.6 1 1.4 db drng alc dynamic range 30 db vcl th voltage control loop reference threshold on v sense pin figure 13 170 190 210 mv pk vcl hyst hysteresis on voltage loop reference threshold figure 13 +-19 mv ccl th current control loop reference threshold on c sense pin figure 13 1.80 1.90 2.00 v ccl hyst hysteresis on voltage loop reference threshold figure 13 210 250 290 mv v sense vsense input impedance 36 k w t rxtx carrier activation time figure 16 - 600 baud xtal=16mhz 0.01 1.6 ms figure 16- 1200 baud xtal=16mhz 0.01 800 m s figure 16- 2400 baud xtal=16mhz 0.01 400 m s figure 16- 4800 baud xtal=16mhz 0.01 200 m s talc carrier stabilization time from step 16 to zero or from step 16 to step 31, figure 16. xtal =16mhz 3.2 ms t st tstep figure 16 xtal =16mhz 200 m s receiver v in input sensitivity (normal mode) 1 2 mv rms input sensitivity (high sens.) 500 m v rms v in maximum input signal 2 v rms r in input impedance 80 100 140 k w v cd carrier detection sensitivity (normal mode) 12v rms carrier detection sensitivity (high sensitivity mode) 500 v rms v bu band in use detection level 77 85 db/ vrms electrical characteristcs (continued) (avcc = dvcc = +5v, pavcc =+9 v, pavss, sgnd = dvss = 0v,-40c tamb 85c, unless otherwise specified) symbol parameter test condition min. typ. max. unit 7/30 st7538 voltage regulator vdc linear regulator output voltage -25 st7538 8/30 zc (high) zero crossing detection high threshold 5 +45 mv zc (offset) zero crossing offset -20 +20 mv operational amplifier c out(sync) max sync current 15 28 45 ma c out(source) max source current -30 -20 -10 ma c in(offset) input terminals offset -38 +38 mv gbwp gain bandwidth product 6 7 9 mhz serial interface ts setup time see figure 3, 5, 6, 7 & 8 5 ns t h hold time see figure 3, 5, 6, 7 & 8 2 ns t cr clr/t vs. reg_data or rxtx see figure 3, 5, 6, 7 & 8 t b /4 t cc clr/t vs. clr/t see figure 3, 5, 6, 7 & 8 t b 2*t b t ds setup time see figure 3, 5, 6, 7 & 8 t b /4 t b /2 t dh hold time see figure 3, 5, 6, 7 & 8 t b /4 t b /2 t crp see figure 4 t h t b /2 electrical characteristcs (continued) (avcc = dvcc = +5v, pavcc =+9 v, pavss, sgnd = dvss = 0v,-40c tamb 85c, unless otherwise specified) symbol parameter test condition min. typ. max. unit 9/30 st7538 functional description carrier frequencies st7538 is a multi frequency device: eight programmable carrier frequencies are available (see table 1). only one carrier could be used a time. the communication channel could be varied during the normal working mode to realize a multifrequency communication. selecting the desired frequency in the control register the transmission and reception filters are accord- ingly tuned. table 1. baud rates st7538 is a multi baud rate device: four baud rate are available (see table 2). table 2. note: 1. default value 2. frequency deviation. 3. deviation = d f / (baud rate) 4. deviation 0.5 not allowed fcarrier f (khz) f0 60 f1 66 f2 72 f3 76 f4 82.05 f5 86 f6 110 f7 (1) 132.5 baud rate [baud] d f (2) (hz) deviation (3) 600 600 1 (4) 1200 600 1200 0.5 1 2400 (1) 1200 (1) 2400 0.5 1 4800 2400 4800 0.5 1 st7538 10/30 mark and space frequencies mark and space communication frequencies are defined by the following formula: f ("0") = fcarrier + [ d f ]/2 f ("1") = fcarrier - [ d f ]/2 d f is the frequency deviation. with deviation = 0.5 the difference in terms of frequency between the mark and space tones is half the baudrate value ( d f =0.5*baudrate). when the deviation = 1 the difference is the baudrate itself ( d f = baudrate). the minimal frequency deviation is 600hz. table 3. carrier frequency (khz) baud rate deviation exact frequency [hz] (clock=16mhz) carrier frequency (khz) baud rate deviation exact frequency [hz] (clock=16mhz) 10 10 60 600 -- 82.05 600 -- 1 59733 60221 1 81706 82357 1200 0.5 59733 60221 1200 0.5 81706 82357 1 59408 60547 1 81380 82682 2400 0.5 59408 60547 2400 0.5 81380 82682 1 58757 61198 1 80892 83171 4800 0.5 58757 61198 4800 0.5 80892 83171 1 57617 62337 1 79590 84473 66 600 -- 86 600 -- 1 65755 66243 1 85775 86263 1200 0.5 65755 66243 1200 0.5 85775 86263 1 65430 66569 1 85449 86589 2400 0.5 65430 66569 2400 0.5 85449 86589 1 64779 67220 1 84798 87240 4800 0.5 64779 67220 4800 0.5 84798 87240 1 63639 68359 1 83659 88379 72 600 -- 110 600 -- 1 71777 72266 1 109701 110352 1200 0.5 71777 72266 1200 0.5 109701 110352 1 71452 72591 1 109375 110677 2400 0.5 71452 72591 2400 0.5 109375 110677 1 70801 73242 1 108724 111165 4800 0.5 70801 73242 4800 0.5 108724 111165 1 69661 74382 1 107585 112467 76 600 -- 132.05 600 -- 1 75684 76335 1 132161 132813 1200 0.5 75684 76335 1200 0.5 132161 132813 1 75358 76660 1 131836 133138 2400 0.5 75358 76660 2400 0.5 131836 133138 1 74870 77148 1 131348 133626 4800 0.5 74870 77148 4800 0.5 131348 133626 1 73568 78451 1 130046 134928 11/30 st7538 host processor interface st7538 exchanges data with the host processor thorough a serial interface. the data transfer is managed by reg_data and rxtx lines, while data are exchanged using rxd, txd and clr/t lines. four are the st7538 working modes: n data reception n data transmission n control register read n control register write reg_data and rxtx lines are level sensitive inputs. table 4. n mains access st7538 features two type of communication interfaces: - asynchronous - synchronous the selection can be done through the internal control register. figure 1. C asynchronous mode. st7538 allows to interface the host controller using a 3 line interface (rxd,txd & rxtx ). data are exchange without any auxiliary clock reference in an asynchronous mode without adding any protocol bits. the host controller has to recover the clock reference in receiving mode and control the bit time in transmission mode. rxd line is forced to a low logic level when no carrier is detected. reg_data rxtx data transmission 0 0 data reception 0 1 control register read 1 1 control register write 1 0 rxd clr/t reg_data rxtx st7538 host controller txd asynchronous data interface rxd clr/t reg_data rxtx st7538 host controller txd synchronous data interface d03in1415 st7538 12/30 C synchronous mode. st7538 allows to interface the host controller using a four lines synchronous interface (rxd,txd, clr/t & rxtx ). st7538 is always the master of the communication and provides the clock reference on clr/t line. when st7538 is in receiving mode an internal pll recovers the clock reference. data on rxd line are stable on clr/t rising edge. when st7538 is in transmitting mode the clock reference is internally generated and data are read on txd line on clr/t rising edge. if rxtx line is set to 1 & reg_data=0 (data reception), st7538 enters in an idle state and clr/t line is forced low. after tcc time the modem starts providing received data on rxd line. if rxtx line is set to 0 & reg_data=0 (data transmission), st7538 d in an idle state and transmission circuitry is switched on. (figure 3). after tcc time the modem starts transmitting data present on txd line (figure 3) . figure 2. figure 3. data reception -> data transmission -> data reception packet mode (only for reception) in packet mode data transmission from st7538 to host controller is done at a higher speed than the mains one. this function could reduce the efficiency of data exchange process because the host control- ler is involved in data reception for a shorter period of time. to achieve this function is enabled an internal auxiliary buffer which stores the incoming bits. the buffer is transferred to the host controller when full at the packet rate. the packet rate is programmable and is related to the mclk clock frequency. the length of the packet can be also programmed through the control register (see table 9) to be 16, 14, 9 or 8 bits. the packet mode to start working needs two levels of enable. one at the control register level the other at the pin level. txd is the pin that if forced high enables the packet mode function. according to when txd is forced high, the next incoming bit is stored inside the internal buffer or delivered on rxd pin. if txd pin is forced low during a rx session the transceiver starts working in bit mode and the content of the packet buffer is deleted. transmitting bit synchronization clr/t rxd clr/t txd receiving bit synchronization t s t h d03in1416 t cc t ds t cr t cr t dh t s t h t b t cc clr_t rxd rxtx txd reg_data d03in1402 bit23 bit22 13/30 st7538 figure 4. packet mode timing control register access the communication with st7538 control register is always synchronous. the access is achieved using the same lines of the mains interface (rxd, txd and clr/t) plus reg_data line. with reg_data = 1 and rxtx =0, the data present on txd are loaded into the control register msb first. the st7538 sampled the txd line on clr/t rising edges. the control register content is updated at the end of the register access section (reg_data falling edge). if more than 24 bits are transferred to st7538 only the latest 24 bits are stored inside the control register. with reg_data = 1 and rxtx =1, the content of the control register is sent on rxd port. the data on rxd are stable on clr/t rising edges msb first. t crp t dh t ds clr_t idle idle idle rxd clr_t rxd txd d03in1406 st7538 14/30 figure 5. data reception control register read data reception timing diagram figure 6. data reception control register write data reception timing diagram figure 7. data transmission control register read data reception timing diagram figure 8. data transmission control register write data reception timing diagram t cc t ds t dh t cr t cr t b t ds t dh t cc clr_t rxd reg_data rxtx d03in1404 bit23 bit22 t cc t cr t cr t cr t cr t b t s t h t dh t ds t cc clr_t rxd rxtx txd reg_data d03in1403 bit23 bit22 t cc t ds t dh t s t h t cr t cr t cr t b t ds t dh t cc clr_t rxd txd reg_data rxtx d03in1405 bit23 bit22 t cc t s t h t ds t cr t cr t cr t dh t s t h t b t cc clr_t txd rxd reg_data rxtx d03in1401 bit23 bit22 15/30 st7538 receiving mode the receive section is active when rxtx pin =1 and reg_data=0. the input signal is read on rai pin using sgnd as ground reference and then pre-filtered by a band pass filter (+-10khz). the pre-filter can be removed setting one bit in the control register. the input stage features a wide dynamic range to receive signal with a very low signal to noise ratio. the amplitude of the applied waveform is automatically adapted by an automatic gain control block (agc) and then filtered by a narrow band band-pass filter centered around the selected channel frequency (+-6k). the result- ing signal is down-converted by a mixer using a sinewave generated by the fsk modulator. finally an intermediate frequency band pass-filter (if filter) improves the signal to noise ration before sending the signal to the fsk demodulator. the fsk demodulator then send the signal to the rx logic for final digital filtering. digital filtering removes noise spikes far from the baud rate frequency and reduces the signal jitter. rxd line is forced at logic level 0 when neither mark or space frequencies are detected on rai pin. mark and space frequency in receiving mode must be distant at least baudrate/2 to have a correct de- modulation. while st7538 is in receiving mode ( rxtx pin =1), the transmit circuitry, power line interface included, are turned off. this allows the device to achieve a very low current consumption (5 ma typ). in receiving mode atop2 pin is internally connected to pavss. n high sensitivity mode it is possible to increase st7538 receiving sensitivity setting to 1 the high sensitivity bit of control register. this function allows to increase the communication reliability when the st7538 sensitivity is the limiting factor. n synchronization recovery system (pll) st7538 embeds a clock recovery system to feature a synchronous data exchange with the host controller. the clock recovery system is realized by means of a second order pll. data on the data line (rxd) are stable on clr/t line rising edge (clr/t falling edge synchronized to rxd line transitions lock-in range). the pll lock-in and lock-out range is p /2. when the pll is in the unlock condition, clr/t and rxd lines are forced to a low logic level. when pll is in unlock condition it is sensitive to rxd rising and falling edges. the maximum number of transition required to reach the lock-in condition is 5. when in lock-in condition the pll is sensitive only to rxd rising edges to reduce the clr/t jitter. st7538 pll is forced in the un-lock condition, when more than 32 equal symbols are received. figure 9. clr/t rxd d03in1417 lock-in range st7538 16/30 n carrier/preamble detection the carrier/preamble block is a digital frequency detector circuit. it can be used to manage the mains access and to detect an incoming signal. two are the possible setting: - carrier detection - preamble detection carrier detection : the carrier/preamble detection block notifies to the host controller the presence of a carrier when it detects on the rai input a signal with an harmonic component close to the programmed carrier frequency. the cd_pd signal sensitivity is identical to the data reception sensitivity (1mvrms typ. in normal sensitivity mode). the cd_pd line is forced to a logic level low when a carrier is detected. preamble detection : the carrier/preamble detection block notifies to the host controller the presence of a carrier modulated at the programmed baud rate for at least 4 consecutive symbols (1010 or 0101 are the symbols sequences detected). cd_pd line is forced low till a carrier signal is detected and pll is in the lock-in range. to reinforce the effectiveness of the information given by cd_pd block, a digital filtering is applied on carrier or preamble notification signal (see control register paragraph). the detection time bits in the control register define the filter performance. increasing the detection time reduced the false notifications caused by noise on main line. the digital filter adds a delay to cd_pd notification equal to the programmed detection time. when the carrier frequency disappears, cd_pd line is held low for a period equal to the detection time and then forced high. figure 10. cd_pd timing during rx figure 11. receiving path block diagram t dcd t cd cd_pd rai d03in1418 low pass band pass pre-filter if filter fsk demodulaor digital filter mixer carrier/ preamble detection agc gain control local osc 32 31 bit 23 bit 0 -2 bit 3,4 &14-21 bit 0-2 rai rxfo bit 9 & 10 bit 12 & 13 carrier detection 3 rxd 8 clr/t 1 cd_pd 9 bu pll bit 3,4 low pass band in use bit 3,4 band pass channel filter band pass d03in1419 17/30 st7538 transmission mode the transmit mode is set when rxtx pin =0 and reg_data pin =0. in transmitting mode the fsk mod- ulator and the power line interface are turned on. the transmit data (txd) enter synchronously or asyn- chronously to the fsk modulator. C host controller synchronous communication mode: on clr/t rising edge, txd line value is read and sent to the fsk modulator. st7538 manage the transmission timing according to the baudrate se- lected C host controller asynchronous communication mode: txd data enter directly to the fsk modulator.the host controller manages the transmission timing in both conditions no protocol bits are added by st7538. the fsk frequencies are synthesized in the fsk modulator from a 16 mhz crystal oscillator by direct dig- ital synthesis technique. the frequencies table in different configuration is reported in table 3. the fre- quencies precision is same as external crystal ones. in the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. the transition between a symbol and the following is done at the end of the on-going half fsk sinewave cycle. figure 12. transmission filter fsk modulator d-type flip flop dac 21 19 8 5 24 7 timer thermal sensor voltage loop current loop clr/t generator zero crossing 23 29 vsense cl atop2 atop1 ato clr/t txd tout 16 15 zcin zcout bit 14 bit 0-5 bit 0-2 bit 7 & 8 band pass pli alc pli pli d03in1420 st7538 18/30 n automatic level control (alc) the automatic level control block (alc) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. the alc gain range is 0db to 30 db and the gain change is clocked at 5khz. each step increases or reduces the voltage of 1db (typ). two are the control loops acting to define the alc gain: - a voltage control loop - a current control loop the voltage control loop acts to keep the peak-to-peak voltage constant on vsense. the gain adjustment is related to the result of a peak detection between the voltage waveform on vsense and two internal voltage references. - if vsense < vcl th - vcl hyst the next gain level is increased by 1 step - if vcl th - vcl hyst < vsense < vcl th + vcl hyst no gain change - if vsense > vcl th + vlc hyst the next gain level is decreased by 1 step the current control loop acts to limit the maximum peak output current inside atop1 and atop2. the current control loop acts through the voltage control loop decreasing the output peak-to-peak amplitude to reduce the current inside the power line interface. the current sensing is done by mirroring the current in the high side mos of the power amplifier (not dissipating current sensing). the output current limit (up to 400mapeak), is set by means of an external resistor (r cl ) connected between cl and pavss. the resistor converts the current sensed into a voltage signal. the peak current sensing block works as the output voltage sensing block: - if v(cl) < ccl th - ccl hyst voltage control loop acting - if ccl th - ccl hyst < v(cl) < ccl th + ccl hyst no gain change - if v(cl) > ccl th + clc hyst the next gain level is decreased by 1 step figure 13 shows the typical connection of current anvoltage control loops. figure 13. voltage and current feedback external interconnection example voltage control loop formula r1 alc voltage loop current loop vsense cl atop/ato vr pk vcl hyst vcl th 1.865v (typ) ccl hyst ccl th avss 5.6nf r2 rcl 100pf vout d03in1421 vr pk r 1 r 2 + r 2 -------------------- vcl th vcl hyst () @ 19/30 st7538 table 5. vout vs. r1 & r2 resistors value notes: the rate of r2 takes in account the input resistance on the sense pin (36 k w ). 5.6nf capacitor effect has been neglected. figure 14. typical output current vs. rcl n integrated power line interface (pli) the power line interface (pli) is a double cmos ab class power amplifier with the two outputs (atop1 and atop2) in opposition of phase. two are the possible configuration: - single ended output (atop1). - bridge connection the bridge connection guarantee a differential output voltage to the load with twice the swing of each individual output. this topology virtually eliminates the even harmonics generation. the pli requires, to ensure a proper operation, a regulated and well filtered supply voltage. pavcc voltage must fulfil the following formula to work without clipping phenomena: to allow the driving of an external power line interface, the output of the alc is available even on ato pin. ato output has a current capability much lower than atop1 and atop2. vout (vrms) vout (db m v) (r1+r2)/r2 r2 (k w ) r1 (k w ) 0.150 103.5 1.1 7.5 1.0 0.250 108.0 1.9 5.1 3.9 0.350 110.9 2.7 3.6 5.6 0.500 114.0 3.7 3.3 8.2 0.625 115.9 4.7 3.3 11.0 0.750 117.5 5.8 2.7 12.0 0.875 118.8 6.6 2.0 11.0 1.000 120.0 7.6 1.6 10.0 1.250 121.9 9.5 1.6 13.0 1.500 123.5 10.8 1.6 15.0 100 125 150 175 200 225 250 275 300 325 irms (ma) 2 2.5 3 3.5 rcl(k w ) d01in1311 4 4.5 5 pavcc vatop ac () 2 ----------------------------------- - 7.5v + 3 st7538 20/30 figure 15. pli bridge topology figure 16. pli startup timing diagram load r1 alc voltage loop current loop vsense cl atop1 vr pk pavss 5.6nf r2 rcl 100pf vout vr pk 2*vr pk inverter atop2 d03in1422 t st 4v 0v t alc t rxtx rx/tx atop2 step number 16 17 18 31 d03in1408 21/30 st7538 control register the st7538 is a multi-channel and multifunction transceiver. an internal 24 bits control register allows to manage all the programmable parameters (table 5). the programmable functions are: n channel frequency n baud rate n deviation n watchdog n transmission timeout n frequency detection time n zero crossing synchronization n detection method n mains interfacing mode n output clock n packet mode baudrate n packet length n packet enable n input pre-filter n sensitivity mode st7538 22/30 table 6. control register functions function value selection note default 0 to 2 frequencies bit2 bit1 bit0 60 khz 66 khz 72 khz 76 khz 82.05 khz 86 khz 110 khz 132.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 132.5 khz 3 to 4 baud rate bit 4 bit 3 600 1,200 2,400 4,800 0 0 1 1 0 1 0 1 2400 5 deviation bit 5 0.5 1 0 1 0.5 6 watchdog bit 6 disabled enabled (1.5 s) 0 1 enabled 7 to 8 transmission time out bit 8 bit 7 disabled 1 s 3 s not used 0 0 1 1 0 1 0 1 1 sec 9 to 10 frequency detection time bit 10 bit 9 500 m s 1 ms 3 ms 5 ms 0 0 1 1 0 1 0 1 1 ms 11 zero crossing synchronization bit 11 disabled enabled 0 1 disabled 23/30 st7538 function value selection note default bit 13 bit 12 12 to 13 detection method carrier detection without conditioning 0 0 carrier detection notification on cd_pd line clr/t and rxd signal always present preamble detection without conditioning carrier detection with conditioning 0 1 clr/t and rxd lines are forced to 0 when carrier is not detected preamble detection without conditioning 1 0 preamble detection notification on cd_pd line clr/t and rxd signal always present preamble detection with conditioning 1 1 preamble detection notification on cd_pd line clr/t and rxd lines are forced to 0 when preamble has not been detected or pll is in unlock condition bit 14 14 mains interfacing mode synchronous asynchronous 0 1 asynchronous bit 16 bit 15 15 to 16 output clock 16 mhz 8 mhz 4 mhz not used 0 0 1 1 0 1 0 1 4 mhz bit 18 bit 17 17 to 18 packet mode baud rate mclk/32 mclk/64 mclk/128 mclk/256 0 0 1 1 0 1 0 1 mlck/64 bit 20 bit 19 19 to 20 packet length 8 bit 9 bit 14 bit 16 bit 0 0 1 1 0 1 0 1 14 bits bit 21 21 packet mode enable disabled enabled 0 1 disabled bit 22 22 sensitivity mode normal sensitivity high sensitivity 0 1 normal bit 23 23 input filter disabled enabled 0 1 disabled table 6. control register functions (continued) st7538 24/30 auxiliary analog and digital functions band in use the band in use block has a carrier detection like function but with a different input sensibility (77db m v typ.) and with a different bandpass filter selectivity (40db/dec). bu line is forced high when a signal in band is detected. to prevent bu line false transition, bu signal is conditioned to carrier detection internal signal. time out time out function is a protection against a too long data transmission. when time out function is enabled after 1 or 3 second of continuos transmission the transceiver is forced in receiving mode. this function allows st7538 to automatically manage the cenelec medium access specification. when a time-out event occur, tout is forced high, and is held high for at least 125 ms. to unlock the time out condition rxtx should be forced high. during the time out period only register access or reception mode are en- abled. during reset sequence if rxtx line =0 & reg_data line =1, timeout protection is suddendly en- abled and st7538 must be configured in data reception after the reset evant before starting a new data transmission. time out time is programmable using control register bits 7 and 8 (table 6). figure 17. time-out timing and unlock sequence reset & watchdog rsto output is a reset generator for the application circuitry. during the st7538 startup sequence is forced low. rsto becomes high after a t rsto delay from the end of oscillator startup sequence. inside st7538 is also embedded a watchdog function. the watchdog function is used to detect the occur- rence of a software fault of the host controller. the watchdog circuitry generates an internal and external reset (rsto low for t rsto time) on expiry of the internal watchdog timer. the watchdog timer reset can be achieved applying a negative transition on wd pin fig 18. figure 18. reset and watchdog timing t out t off t offd clr_t txd d03in1409 t out t rsto t wd t wm t rsto mclk rsto wd d03in1410 25/30 st7538 zero crossing detection the mains voltage zero crossing can be detected, through a proper connection of zcin to the mains. zcin comparator has a threshold fixed at sgnd. zcout is a ttl output forced high after a positive zero-crossing transition, and low after a negative one. setting the bit 11 inside the control register to 1 the transmission is automatically synchronized to the mains positive zero-crossing transition. this function is achieved turning on the pli when rx/tx is low and delaying the clr/t first transition until the first zero-crossing event. the automatic synchronization procedure can work only if the synchronous interface is programmed. if asynchronous interface is in use the zero crossing synchronization can be achieved managing the zcout line. figure 19. synchronous zero-crossing transmission output clock mclk is the master clock output. the clock frequency sourced can be programed through the control reg- ister to be a ratio of the crystal oscillator frequency (fosc, fosc/2 fosc/4). the transition between one fre- quency and another is done only at the end of the ongoing cycle. reg ok regok allows to detect an undesired modification of the control register content. regok function is dis- abled during a control register writing session. under voltage lock out the uvlo function turns off the device if the pavdd voltage falls under 4v. hysteresis is 250mv typically. thermal shutdown the st7538 is provided of a thermal protection which turn off the pli when the junction temperature ex- ceeds 170c 10% . hysteresis is around 30c. when shutdown threshold is overcome, pli interface is switched off. thermal shutdown event is notified to the host controller using timeout line. when timeout line is high, st7538 junction temperature exceed the shutdown threshold (not lached). 5v voltage regulator and power good function st7538 has an embedded 5v linear regulator externally available to supply the application circuitry. the linear regulator has a very low quiescent current (50 m a) and a current capability of 100ma. the reg- ulator is protected against short circuitry events. when the regulator voltage is above the power good threshold (v pg) , power good line is forced high, while is forced low at startup and when vdc falls below v pg - v pghys voltage. t zcin rxtx clr/t txd zcout zc del d03in1423 st7538 26/30 figure 20. power good function power-up procedure to ensure st7538 proper power-up sequence, pavcc, avss and dvss supply has to fulfil the following rules: pavcc rising slope must not exceed 10v/ms. when dvdd and avdd are below 5v: 100mv < pavcc-avdd , pavcc-dvdd < 1.2v. when avdd and dvdd supply are connected to vdc the above mentioned relation is guarantied if vdc load < 100ma and if the filtering capacitor on vdc < 100uf. figure 21. power-up sequence package information best thermal performance is acheived when slug is soldered to pcb. it is recomended to have five solder dots (see fig. 22) without resist to connect the copper slug to the ground layer on the soldering side. moreover it is recomeded to connect the ground layer on the soldering side to another ground layer on the opposite side with 15 to 20 vias. pg ok 250mv time time v dc 4.5v pg d03in1411 voltage time 5v pavcc-avdd pavcc-dvdd pavcc dvdd, avdd d03in1424 27/30 st7538 figure 22. application schematic example with coupling tranformer. st7538 pg regok wd rxd rx/tx reg/data txd clr/t cd/pd bu tout mclk rsto zcout atop2 pavcc 21 22 xin 27 xout 26 zcin 16 vsense cl atop1 19 23 ato 24 29 13 test3 30 test2 35 test1 rai 32 rxfo 31 10 dvdd 28 avdd 33 vdc c_plus 38 c_minus 37 c_out 40 14 36 42 1 3 4 5 7 8 9 11 12 15 43 2 dvss gnd 6 17 n.c. dvss 18 20 pavss sgnd 25 34 n.c. 39 n.c. gnd 41 44 n.c. ac/dc converter host controller ac line zero crossing transmission synchronization no external components for power line driver single suppy 5v supply for host controller clock & reset for host controller 5 lines serial interface voltage regulation & current protection load r1 r2 rcl c1 c2 d03in1412 st7538 28/30 figure 23. st7538 slug drawing figure 24. soldering information copper slug solder plated lead frame 0.10mm 0.05 d03in1414 ll1 l a b l1 solder dots cu plate d03in141 3 package sizes 10x10x1.4mm a 2.00 mm b 1.00 mm l 6.00 mm l1 (copper plate) 10.00 mm if pcb with ground layer, connect copper plate with 15 to 20 vias 29/30 st7538 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.014 0.018 c 0.09 0.20 0.003 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 0.80 0.031 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 h 5.89 0.232 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 s 6.00 0.236 s1 6.00 0.236 k 0? (min.), 3.5? (typ.), 7?(max.) ccc 0.10 0.004 tqfp44 (10x10x1.40mm) with slug down 0049510 d information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 30/30 st7538 |
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